As the scaling of semiconductor devices continues into the nanometer regime there is an ever increasing search for new and improved nanostructures for replacing conventional devices and technologies. Many methods of fabricating nanostructures are known in the literature.
For example, U.S. Pat. No. 7,687,876 discloses a method for fabricating nanostructures where several intermediate layers are deposited on a substrate followed by a catalyst layer from which nanostructures are grown. Through the provision of a multi-layer stack between the substrate and the catalyst layer, the morphology as well as the electrical properties of the nanostructures can be tailored to a wide variety of applications. For certain applications, where such an extensive tailoring capability may not be required, it would be desirable to reduce the number of process steps involved in forming the nanostructures.